102
9151AINDCO07/09
ATA8742
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at BOTTOM. See Fast PWM Mode on
page 95 for more details.
Table 20-4 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP . See Phase Correct PWM Mode on
page 97 for more details.
" Bits 3, 2 Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
" Bits 1:0 WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 20-8 on page 102. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode,
and two types of Pulse Width Modulation (PWM) modes (see Modes of Operation on page 94).
Note:
1. MAX = 0xFF
BOTTOM = 0x00
Table 20-7. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0A1
COM0A0
Description
0
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1
1
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Table 20-8. Waveform Generation Mode Bit Description
Mode
WGM2
WGM1
WGM0
Timer/Counter
Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on
(1)
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
BOTTOM
MAX
4
1
0
0
Reserved
5
1
0
1
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
1
1
0
Reserved
7
1
1
1
Fast PWM
OCRA
BOTTOM
TOP
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